Posts Tagged ‘OpenOCD’

Enabling working area in SDRAM for OpenOCD on PXA255

Thursday, February 7th, 2008

Flash memory operations (programming, erasing and reading) on PXA targets without using some on board memory for a working area are painfully slow. How painful? Try 29 minutes just to program a 112K U-boot file. However, using some on-board working memory reduced the programming time to 6 seconds. I suppose that’s a significant increase! The PXA270 has some internal static memory that can be used as the working area, but there are still a lot of PXA255 systems kicking about which have no processor memory, and so the system memory needs to be initialized at startup in order to use some of it for the OpenOCD working area.

The normal config file used with the openocd daemon has a couple of tricky items. See the comments in my openocd.cfg file below. This is the config file I use for my PXA255 targets:

# Olimex OpenOCD config file for Intel PXA255 or 270
# Hacked together 2008-02-07 by Jeff Sutherland, FOM Sytems, Inc.
# Note script needed for pxa255 in order to init target SDRAM for flash ops.
# use internal SRAM on the 270 for working area or optionally set up the SDRAM
telnet_port 3333
gdb_port 4444
interface ft2232
ft2232_layout olimex-jtag
ft2232_vid_pid 0x15BA 0x0004
ft2232_device_desc "Olimex OpenOCD JTAG TINY"
jtag_speed 1
# set jtag_nsrst_delay to the delay introduced by your reset circuit
# the rest of the needed delays are built into the openocd program
jtag_nsrst_delay 250
# set the jtag_ntrst_delay to the delay introduced by a reset circuit
# the rest of the needed delays are built into the openocd program
jtag_ntrst_delay 250

#use combined on interfaces or targets that can't set TRST/SRST separately
#but don't try running scripts on targets with resets tied together :-(
reset_config trst_and_srst separate

#jtag scan chain

#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
#This is for pxa27x:
#jtag_device 7 0x1 0x7f 0x7e
#This is for pxa255:
jtag_device 5 0x1 0x1f 0x1e

#target configuration
daemon_startup reset

#target xscale little reset_halt 0 pxa27x
target xscale little run_and_init 0 pxa255
#NOTE: run_and_init is the only option that will work with a script

#pxa255 sdram initialization script:
target_script 0 reset pxa255.scr

# use internal RAM on pxa27x or tweak script to init target SDRAM.
# If you are using a PXA255 you MUST initialize SDRAM or leave this option off
working_area 0 0xa0000000 0x10000 nobackup

run_and_halt_time 0 30

#flash bank
# works for P30 flash as well as J3C/J3D strataflash parts
# Note we normally have 2 28F128J3D's for 32 bit wide flash memory.
flash bank cfi 0x00000000 0x1000000 2 4 0

Note that the target line refers to a script file called px255.scr. This is a script file containing openOCD commands which initialize the memory. Any valid openOCD commands may be used here but probably memory read and memory write will be the only ones you ever need. Here is my pxa255.scr file:

# pxa255.scr - openOCD script to initialize system and local SDRAM to greatly
# aid performance whilst flashing and dumping meomory.
#-----------------------------------------------------
# setup GPIO
#
#mww 0x40E00018 0x00008000 ;CPSR0
#mww 0x40E0001C 0x003FAB82 ;GPSR1
#mww 0x40E00020 0x0001C000 ;GPSR2
#mww 0x40E00024 0x000B2150 ;GPCR0
#mww 0x40E00028 0xFCC00050 ;GPCR1
#mww 0x40E0002C 0x00003FFF ;GPCR2
#mww 0x40E0000C 0xC38BA150 ;GPDR0
#mww 0x40E00010 0xFCFFABD2 ;GPDR1
#mww 0x40E00014 0x0001FFFF ;GPDR2
#mww 0x40E00054 0x80011004 ;GAFR0_L
#mww 0x40E00058 0xA51A800A ;GAFR0_H
#mww 0x40E0005C 0x69908018 ;GAFR1_L
#mww 0x40E00060 0xAAA5AAAA ;GAFR1_H
#mww 0x40E00064 0xAAAAAAAA ;GAFR2_L
#mww 0x40E00068 0x00000002 ;GAFR2_H
#mww 0x40F00004 0x00000030 ;PSSR# setup memory controller
# Local tweaks here for Falcon II board
# This board uses 2 13x9 sdrams for a 32 bit wide data bus#msc1
mww 0x4800000C 0x3FC43FCC
#msc0
mww 0x48000008 0x3FC423F2
#msc1
mww 0x4800000C 0x3FC43FCC
#msc2
mww 0x48000010 0x3FC43FC4
#mecr
mww 0x48000014 0x00000000
#mcmem0
mww 0x48000028 0x00010504
#mcmem1
mww 0x4800002C 0x00010504
#mcatt0
mww 0x48000030 0x00010504
#mcatt1
mww 0x48000034 0x00010504
#mcio0
mww 0x48000038 0x00004715
#mcio1
mww 0x4800003C 0x00004715

#mdref
mww 0x48000004 0x03CA4018
#mdref
mww 0x48000004 0x004B4018
#mdref
mww 0x48000004 0x000B4018
#mdref
mww 0x48000004 0x000BC018
#mdcnfg
mww 0x48000000 0x00001AC8

#DELAY 20 maybe put dummy mdw commands here???
mdw 0x00000000 20
#wakeup the sdram:
mww 0xA0000000 0xA0000000
mww 0xA0000000 0xA0000000
mww 0xA0000000 0xA0000000
mww 0xA0000000 0xA0000000
mww 0xA0000000 0xA0000000
mww 0xA0000000 0xA0000000
mww 0xA0000000 0xA0000000
mww 0xA0000000 0xA0000000
#mdcnfg
mww 0x48000000 0x00001AC9
#mdmrs
mww 0x48000040 0x00000000

Once you start the openocd daemon it will automatically run this script after initalizing the processor. Test some of the memory starting at 0xa0000000 to see if the memory truly activated.